The present inventive concept relates to a semiconductor package and method of fabricating the same, and more particularly to a semiconductor chip stack-type package and method of fabricating the same.
As electrical devices are becoming lighter, thinner, shorter and smaller, the level of integration and mounting rate are becoming increasingly important considerations in the design of packages for electrical devices. Also, in computers, the size of installed semiconductor devices, such as Random Access Memory (RAM) devices and flash memory devices, is increasing due to an increase of memory capacity. On the other hand, the size of the package is becoming smaller due to the above reasons.
Various schemes to decrease package size have been introduced including, for example: a stack-type semiconductor package in which a plurality of semiconductor chips or semiconductor device packages are stacked; and a semiconductor module in which a plurality of semiconductor chips, a plurality of semiconductor device packages and/or a plurality of stack-type semiconductor packages are mounted in each level on at least one surface of a Printed Circuit Board (PCB).
These packages may be classified into multi-chip packages (MCP), in which a plurality of semiconductor chips with different functions are mounted (or stacked), and semiconductor chip stack-type packages, such as a quad die package (QDP) and an octad die package (ODP), in which a plurality of semiconductor chips are stacked in order to realize high capacity. In addition, a package in which the above two types are both incorporated is being developed.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor chip stack-type package.
Referring to FIG. 1, a semiconductor chip stack-type package includes a lead frame, semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld, bonding wires 25ua, 25ub, 25uc, 25ud, 25la, 25lb, 25lc and 25ld, and a molded portion 40.
The lead frame includes a die paddle part 20p and a lead part 20l. The die paddle part 20p provides a mounting region for mounting a semiconductor chip. The semiconductor chip is mounted on an upper surface and/or a lower surface of the die paddle part 20p. The lead part 20l is electrically connected to the semiconductor chips mounted on the die paddle part 20p by bonding wires, to provide electrical connection between an external circuit (not shown) such as a Printed Circuit Board (PCB) and the semiconductor chips.
The semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld include upper semiconductor chips 10ua, 10ub, 10uc and 10ud stacked on the upper surface of the die paddle part 20p respectively, and lower semiconductor chips 10la, 10lb, 10lc and 10ld stacked on the lower surface respectively.
Adhesive material layers (not shown) are included between the upper semiconductor chips 10ua, 10ub, 10uc and 10ud, the lower semiconductor chips 10la, 10lb, 10lc and 10ld and the die paddle part 20p of the lead frame. Also, adhesive material layers (not shown) are further provided between each of the semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld. The upper semiconductor chips 10ua, 10ub, 10uc and 10ud and the lower semiconductor chips 10la, 10lb, 10lc and 10ld are mounted on the upper and lower surfaces of the die paddle part 20p by means of the adhesive material layers.
Inter-chip material layers 15ua, 15ub, 15uc, 15la, 15lb and 15lc are interposed between the semiconductor chips adjacent to each other included in the semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld. These inter-chip material layers 15ua, 15ub, 15uc, 15la, 15lb and 15lc between the semiconductor chips are formed to provide space (or height) for the bonding wires 25ua, 25ub, 25uc, 25ud, 25la, 25lb, 25lc and 25ld. The bonding wires 25ua, 25ub, 25uc, 25ud, 25la, 25lb, 25c and 25ld electrically connect the semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld and the lead part 20l, respectively.
The bonding wires 25ua, 25ub, 25uc, 25ud, 25la, 25lb, 25lc and 25ld electrically connect bonding pads (not shown) of each of the semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld to the lead part 20l of lead frame.
The molded portion 40 encapsulates the die paddle part 20p, inner leads of the lead part 20l adjacent to the die paddle part 20p, the semiconductor chips 10ua, 10ub, 10uc, 10ud, 10la, 10lb, 10lc and 10ld, and the bonding wires 25ua, 25ub, 25uc, 25ud, 25la, 25lb, 25lc and 25ld. The outer leads of the lead part 20l, which are outside of the molded portion 40, function as terminals that electrically connect the semiconductor chip stack-type package to an external circuit.
According to the trend toward higher capacity of electrical devices, when large-sized semiconductor chips are stacked, the above-described semiconductor chip stack-type package has shorter inner leads in a limited package space. Accordingly, it becomes increasingly difficult to provide enough space for bonding wires that electrically connect semiconductor chips and the lead part.